Recent semiconductor devices require data transfer at increasingly higher speed. For example, due to an increase in the display resolution of portable terminals, the data transmission rate of image data to a display driver which drives a display panel (e.g., a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) panel, and so forth) has been increasingly increased.
One technique commonly used in high-speed data transmission is clock embedding, which involves embedding a clock in a data signal; however, clock embedding requires circuits which consume relatively large electric power, such as PLL (phase locked loop) circuits and DLL (delay locked loop) circuits.
From this background, a battery-powered appliance, such as a portable terminal, often uses an architecture in which a data signal and a clock signal are transmitted over separate transmission lines, without using clock embedding. For example, the Mobile Industry Processor Interface (MIPI) D-PHY specification, which has been standardized by the MIPI Alliance, uses an architecture in which a data signal and a clock signal are transmitted over separate transmission lines.
In a data transmission system using such an architecture, the phases of the data signal and the clock signal are designed to provide a sufficient margin for the setup time and hold time, which are determined by the design of the receiving side.
FIG. 1A illustrates an example of the phases of a data signal and a clock signal. Data transfer is considered stable when the sum of the setup time and the hold time is sufficiently short with respect to a UI (unit interval), which is the unit time of the data transfer. The time difference tUI−(tSETUP+tHOLD) is the time margin acceptable in the design, where tUI is the time duration of one UI, tSETUP is the setup time and tHOLD is the hold time. FIG. 1A illustrates the case when the sum of the setup time and the hold time is sufficiently short for one UI.
A part of the time margin may be allocated to compensation of design variations in the transmitting-side device and the receiving-side device; however when data transfer is performed at a high data rate in a data transfer system in which a data signal and a clock signal are transmitted over separate transmission lines, a major part of the time margin is used to acquire a design margin of the transmission lines, that is, to address the skew between the data signal and the clock signal.
Overall, two types of factors are known which cause the skew between a data signal and a clock signal. A first factor is the timing difference caused by the difference in the transmission line length between the data signal and the clock signal. The difference in the transmission line length is one major factor of the skew; this has been conventionally addressed by equal-length wiring. A second factor is waveform distortion caused by the frequency characteristics of the transmission lines, called ISI (inter-symbol interference). When the data transmission rate is increased, the skew caused by factor(s) other than the difference in the transmission line length, such as ISI, may be significant. This undesirably makes it difficult to design transmission lines.
Especially, 4K/2K display technologies and high-frame rate technologies have been recently developed, and use of these technologies is accompanied by a rapid increase in the transmission rate of image data. An increase in in the data transmission rate causes a reduction in the time duration of one UI and this undesirably decreases the time margin as illustrated in FIG. 1B. Conventionally, the reduction of the time duration of one UI have been addressed by reductions in the setup time and the hold time through the microfabrication of the semiconductor device; however, recent increases in the data transmission rate have made it difficult to maintain the time margin for achieving stable data transfer, only by reducing in the setup time and the hold time through the semiconductor device microfabrication.
From this background, there is a need for a technique for compensating the skew between a data signal and a clock signal in a data transfer system in which the data signal and the clock signal are transmitted over separate transmission lines.
Note that Japanese patent application publication No. 2014-168195 A discloses a technique for eliminating the skew. The receiver device disclosed in this patent document is configured to control the delay time of a variable delay circuit which delays at least one of a clock signal and a data signal, in response to skew detection data generated by a skew detection circuit.